The present invention relates to charge pumps for use in integrated circuits. More particularly, the present invention relates to a charge pump having a circuit for controlling the charging current of the charge pump.
The demand for less expensive, and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications continues to increase rapidly. As a result, integrated circuit manufacturers are requiring improved performance in the voltage supplies and references for such components and devices to meet the design requirements of such emerging applications.
One device utilized for providing a regulated voltage supply is a charge pump circuit. Charge pumps are DC/DC converters that utilize a capacitor instead of an inductor or transformer for energy storage, and are configured for generating positive or negative voltages from the input voltage. Charge pumps can be configured in various manners, including a charge pump voltage doubler circuit, i.e., a charge pump circuit configured for doubling the input voltage, as well as tripler and inverter configurations. These charge pumps can operate to multiply the input voltage by some factor, such as by one-half, two, or three times or any other suitable factor of the input voltage, to generate the desired output voltage. In addition, charge pump circuits can be configured for single phase regulation, with a single charge pump capacitor used to charge current during one phase of operation and discharge current during another phase of operation, or for dual phase regulation, in which two charge pump capacitors are configured to operate during both phases of operation, i.e., one of the capacitors is charging current and the other capacitor is discharging current during each phase of operation.
Charge pumps typically utilize transistors and/or diodes as switching devices to provide current paths for charge transfer. On occasions when the sum of any residual voltages of the charging capacitors in a charging/discharging circuit loop is smaller than the voltage of the power supply, a significantly large amount of transient current tends to flow within the loop. Further, an uncontrolled peak current occurring during charging or discharging of the capacitors is only limited by the xe2x80x9con-resistancexe2x80x9d of the switching devices and the equivalent series resistance (ESR) of the capacitors. Moreover, the uncontrolled alternating peak current generally flows out of the positive power supply and into the negative power supply, e.g., into ground, thus causing significantly large electromagnetic interference (EMI) to associated electronic circuits. Still further, the large uncontrolled current also tends to charge the output reservoir capacitor which results in large voltage ripples at the output of the charge pump.
With reference to FIG. 1, a charge pump regulator circuit 100 configured for dual phase voltage regulation is illustrated. Charge pump regulator circuit 100 includes a charge pump control circuit 102 comprising four switches S1, S2, S3 and S4 and a first pump capacitor CPUMP configured for supplying current to a load device during a first phase, and four switches S1xe2x80x2, S2xe2x80x2, S3xe2x80x2 and S4xe2x80x2 and a second pump capacitor CPUMPxe2x80x2 configured for supplying current to a load device during a second phase. In addition, charge pump circuit 100 comprises a reservoir capacitor CRES for maintaining charge to a load device RLOAD to facilitate regulation of output voltage VOUT. A pass device M1 is coupled between a supply voltage VIN and switches S1 and S1xe2x80x2 for regulating output voltage VOUT by controlling the output current, e.g., by controlling the discharging current of first pump capacitor CPUMP and second pump capacitor CPUMPxe2x80x2. For example, for a discharging current of 5 mA alternating from each of first pump capacitor CPUMP and second pump capacitor CPUMPxe2x80x2, an average total output current of 5 mA can be realized. As a result of the dual phase regulation, output voltage VOUT can be configured to be approximately twice the voltage at a node A, i.e., the voltage at the drain of pass device M1. However, the charging currents of first pump capacitor CPUMP and second pump capacitor CPUMPxe2x80x2 are determined only by the difference between a supply voltage VIN and the residual voltage of capacitors CPUMP and CPUMPxe2x80x2, the on-resistance of switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2, and the ESR of capacitors CPUMP and CPUMPxe2x80x2.
Charge pump circuit 100 is typically controlled by a clock having a 50% duty cycle, i.e., a clock having a clock phase-one and phase-two. During clock phase-one, switches S1 and S4 are closed to allow current to flow through pass device M1, switch S1, a pre-charged capacitor CPUMP, and switch S4 to load device RLOAD, while switches S2 and S3 remain in an xe2x80x9coffxe2x80x9d condition. Meanwhile, switches S2xe2x80x2 and S3xe2x80x2 are closed to allow charging current to flow through switches S2xe2x80x2 and S3xe2x80x2 such that pump capacitor CPUMPxe2x80x2 is pre-charged to approximately the supply voltage VIN, while switches S1xe2x80x2 and S4xe2x80x2 remain in an xe2x80x9coffxe2x80x9d condition, i.e., opened. During clock phase-two, switches S1xe2x80x2 and S4xe2x80x2 are closed to allow current to flow through pass device M1, switch S1xe2x80x2, charged capacitor CPUMPxe2x80x2, and switch S4xe2x80x2, to load device RLOAD, while switches S2xe2x80x2 and S3xe2x80x2 are opened. Meanwhile, switches S2 and S3 are closed to allow re-charging current to flow through switches S2 and S3 such that pump capacitor CPUMP is again pre-charged to approximately the supply voltage VIN, while switches S1 and S4 are opened. The above dual phase operation suitably repeats at a fixed frequency controlled by the clock.
The current through pass device M1 for regulation of output voltage VOUT, i.e., the output or discharging current, is controlled by adjusting the gate voltage VC of pass device M1. For example, with reference to FIG. 2, a voltage regulator circuit 200 comprising a charge pump control circuit 202 and an error amplifier 204 can be configured with a negative feedback control loop to provide an output voltage VOUT approximately equal to two times the voltage VA at node A, i.e., a voltage 2VA. Error amplifier 204 is configured to receive a voltage reference VREF and a feedback signal VFB through feedback resistor network comprising resistors R1 and R2. Accordingly, error amplifier 204 can control gate voltage VC, and thus enabling pass device to facilitate regulation of output voltage VOUT through regulation of the voltage VA at node A.
However, the recharging or inrush current is only limited by the on-resistance of switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2. The selection of the on-resistance for switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2 is difficult, in that while switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2 generally need to be configured to provide a high enough on-resistance to limit any inrush current, switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2 must also be configured to provide a low enough on-resistance to output sufficient current at a low level of supply voltage VIN. Due to the concurrent need to provide such a low enough on-resistance, a large inrush of current can occur during the closing of switches S2 and S3 and switches S2xe2x80x2 and S3xe2x80x2, for example up to ten times the average output current, thus resulting in conductive noise within the charge pump circuit 100.
Moreover, as the supply voltage VIN increases from a low level to a high level, the on-resistance of switches S1, S2, S3 and S4 tends to decrease to a very low level due to a higher gate driving voltage. Accordingly, the current flowing through, i.e., the current flowing to ground and to capacitor CRES, becomes excessively large, thus resulting in uncontrolled electromagnetic interference (EMI) with other associate electronic devices in the forms of both conduction and radiation.
Still further, due to large transient currents flowing through the wirebond between the silicon and the lead frame, a high slew rate of current change is realized, thus inducing voltage spikes across the wirebonds. Accordingly, these voltage spikes induce errors within any internal precision analog circuitry, thus generating output voltage ripple and noise at the output of the charge pump regulator.
In accordance with various aspects of the present invention, a charge pump circuit is configured for suitably controlling the charging current in the charge pump capacitors. In accordance with an exemplary embodiment, the charge pump circuit is suitably configured with an input current controlling circuit comprising a current limiting device for controlling the inrush current, and thus the charging current in the charge pump capacitors. The input current controlling circuit is configured to regulate the current flowing through the current limiting device to correspond to the current flowing through a pass device configured for regulating the output current. Accordingly, the total input current, and thus the charging current in the charge pump capacitors, can be suitably controlled at all times to significantly reduce the impact of any instantaneous charging currents.